Invention Grant
- Patent Title: Low on-resistance lateral double-diffused MOS device
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Application No.: US13100449Application Date: 2011-05-04
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Publication No.: US08125031B2Publication Date: 2012-02-28
- Inventor: Hsueh-I Huang , Chien-Wen Chu , Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
- Applicant: Hsueh-I Huang , Chien-Wen Chu , Cheng-Chi Lin , Shih-Chin Lien , Chin-Pen Yeh , Shyi-Yuan Wu
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Main IPC: H01L29/02
- IPC: H01L29/02

Abstract:
A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.
Public/Granted literature
- US08362558B2 Low on-resistance lateral double-diffused MOS device Public/Granted day:2013-01-29
Information query
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