An interconnect routing for a card or interposer or the like, including splines of traces on a first layer and traces on a second layer, with vias connecting between the layers. Outer rows of signals are routed out from a chip on the first layer, while inner rows of signals are viad down to the second layer where they are routed out, then viad back up to the first layer. These outer vias are arranged in an arc, enabling the second layer trace segments to be of a more uniform length. The second layer may also include ground or power plane fingers extending between the splines and viad up to ground or power signals of the chip.