There is provided a solid-state imaging device in which images can be read at high speed. Since an n-th processing circuit (e.g. PU1) can be connected to n-th pixel columns (N1) in respective imaging blocks B1, B2, and B3 via switches Q (1), Q (4), and Q (7), signals from the adjacent pixel columns (N2) are to be processed separately by another processing circuit (PU2) even when a partial readout area R may be small. In addition, an image data arithmetic section 10 specifies the partial readout area R restrictively, which allows for higher speed imaging.