A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/output circuit includes a main amplifier that amplifies data written into selected memory cells in the memory cell array during data write operation and that amplifies data read from the selected memory cells during read operation, and a memory element provided accompanying the main amplifier in order to repair a defective memory cell in the memory cell array. The test circuit starts up in test mode, writes data into the memory element through the data input/output terminal, and read data from the memory element into the data input/output terminal regardless of access address information to the memory cell.