An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage.