Invention Grant
- Patent Title: Wake-and-go mechanism with system address bus transaction master
- Patent Title (中): 具有系统地址总线事务主机的唤醒机制
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Application No.: US12024242Application Date: 2008-02-01
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Publication No.: US08127080B2Publication Date: 2012-02-28
- Inventor: Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
- Applicant: Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen R. Tkacs; Stephen J. Walder, Jr.; Matthew B. Talpis
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.
Public/Granted literature
- US20100287341A1 Wake-and-Go Mechanism with System Address Bus Transaction Master Public/Granted day:2010-11-11
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