Invention Grant
US08127080B2 Wake-and-go mechanism with system address bus transaction master 有权
具有系统地址总线事务主机的唤醒机制

Wake-and-go mechanism with system address bus transaction master
Abstract:
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address and snoops the target address on the system bus.
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