Invention Grant
- Patent Title: Electrolytic depositon and via filling in coreless substrate processing
- Patent Title (中): 电解沉积和通孔填充无芯衬底加工
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Application No.: US12890662Application Date: 2010-09-25
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Publication No.: US08127979B1Publication Date: 2012-03-06
- Inventor: Tao Wu , Nicolas R. Watts
- Applicant: Tao Wu , Nicolas R. Watts
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes & Victor LLP
- Agent Alan S. Raynes
- Main IPC: B23K31/02
- IPC: B23K31/02 ; C23D5/02

Abstract:
Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.
Public/Granted literature
- US20120074209A1 ELECTROLYTIC DEPOSITON AND VIA FILLING IN CORELESS SUBSTRATE PROCESSING Public/Granted day:2012-03-29
Information query
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