Invention Grant
US08129256B2 3D integrated circuit device fabrication with precisely controllable substrate removal
有权
3D集成电路器件制造具有精确可控的衬底去除
- Patent Title: 3D integrated circuit device fabrication with precisely controllable substrate removal
- Patent Title (中): 3D集成电路器件制造具有精确可控的衬底去除
-
Application No.: US12194065Application Date: 2008-08-19
-
Publication No.: US08129256B2Publication Date: 2012-03-06
- Inventor: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
- Applicant: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini & Bianco PL
- Agent Stephen Bongini
- Main IPC: H01L21/30
- IPC: H01L21/30

Abstract:
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
Public/Granted literature
- US20100044826A1 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL Public/Granted day:2010-02-25
Information query
IPC分类: