Invention Grant
US08129754B2 Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends
有权
具有栅极电极级的集成电路，其包括至少六个线性形状的导电结构，其形成具有至少一对具有偏移端的线性导电结构的转移器的栅电极
- Patent Title: Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends
- Patent Title (中): 具有栅极电极级的集成电路，其包括至少六个线性形状的导电结构，其形成具有至少一对具有偏移端的线性导电结构的转移器的栅电极
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Application No.: US12571343Application Date: 2009-09-30
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Publication No.: US08129754B2Publication Date: 2012-03-06
- Inventor: Scott T. Becker , Michael C. Smayling
- Applicant: Scott T. Becker , Michael C. Smayling
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L27/10
- IPC: H01L27/10
Abstract:
A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. The cell also includes a number of interconnect levels formed above the gate electrode level.
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