Invention Grant
US08129833B2 Stacked integrated circuit packages that include monolithic conductive vias
有权
堆叠的集成电路封装,包括单片导电通孔
- Patent Title: Stacked integrated circuit packages that include monolithic conductive vias
- Patent Title (中): 堆叠的集成电路封装,包括单片导电通孔
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Application No.: US12606799Application Date: 2009-10-27
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Publication No.: US08129833B2Publication Date: 2012-03-06
- Inventor: Pil-kyu Kang , Jung-Ho Kim , Jong-Wook Lee , Seung-woo Choi , Dae-Lok Bae
- Applicant: Pil-kyu Kang , Jung-Ho Kim , Jong-Wook Lee , Seung-woo Choi , Dae-Lok Bae
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2008-0107855 20081031
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/053 ; H01L23/12 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L27/10 ; H01L29/74

Abstract:
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
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