Invention Grant
US08129833B2 Stacked integrated circuit packages that include monolithic conductive vias 有权
堆叠的集成电路封装,包括单片导电通孔

Stacked integrated circuit packages that include monolithic conductive vias
Abstract:
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
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