Invention Grant
- Patent Title: Techniques for providing reduced duty cycle distortion
- Patent Title (中): 提供减少占空比失真的技术
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Application No.: US12642502Application Date: 2009-12-18
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Publication No.: US08130016B2Publication Date: 2012-03-06
- Inventor: Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
- Applicant: Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent Steven J. Cahill
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.
Public/Granted literature
- US20110074477A1 Techniques for Providing Reduced Duty Cycle Distortion Public/Granted day:2011-03-31
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