Invention Grant
- Patent Title: Methods and devices for leakage current reduction
- Patent Title (中): 泄漏电流降低的方法和装置
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Application No.: US12799910Application Date: 2010-05-03
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Publication No.: US08130042B2Publication Date: 2012-03-06
- Inventor: Jaroslaw Adamski , Daniel Losser , Vikas Sharma
- Applicant: Jaroslaw Adamski , Daniel Losser , Vikas Sharma
- Applicant Address: US CA San Diego
- Assignee: Peregrine Semiconductor Corporation
- Current Assignee: Peregrine Semiconductor Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jacquez & Associates
- Agent Martin J. Jaquez, Esq.; Alessandro Steinfl, Esq.
- Main IPC: H03F3/04
- IPC: H03F3/04
Abstract:
Methods and devices for leakage current reduction are described. A regulator transistor is connected to a switch to bias the transistor with a first voltage during an ON state and a second voltage during the OFF state of the transistor. The switchable bias allows leakage current decrease and “on” resistance increase of the transistor.
Public/Granted literature
- US20100308919A1 Methods and devices for leakage current reduction Public/Granted day:2010-12-09
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