Invention Grant
- Patent Title: Low power memory array column redundancy mechanism
- Patent Title (中): 低功耗内存阵列列冗余机制
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Application No.: US12729489Application Date: 2010-03-23
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Publication No.: US08130572B2Publication Date: 2012-03-06
- Inventor: Greg M. Hess
- Applicant: Greg M. Hess
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Lawrence J. Merkel; Stephen J. Curran
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns.
Public/Granted literature
- US20110235447A1 LOW POWER MEMORY ARRAY COLUMN REDUNDANCY MECHANISM Public/Granted day:2011-09-29
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