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US08130572B2 Low power memory array column redundancy mechanism 有权
低功耗内存阵列列冗余机制

Low power memory array column redundancy mechanism
Abstract:
A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns.
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