Invention Grant
US08131535B2 Translation block invalidation prehints in emulation of a target system on a host system
有权
主机系统上的目标系统仿真中的翻译块无效预处理
- Patent Title: Translation block invalidation prehints in emulation of a target system on a host system
- Patent Title (中): 主机系统上的目标系统仿真中的翻译块无效预处理
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Application No.: US13153129Application Date: 2011-06-03
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Publication No.: US08131535B2Publication Date: 2012-03-06
- Inventor: Stewart Sargaison , Victor Suba
- Applicant: Stewart Sargaison , Victor Suba
- Applicant Address: JP Tokyo
- Assignee: Sony Computer Entertainment Inc.
- Current Assignee: Sony Computer Entertainment Inc.
- Current Assignee Address: JP Tokyo
- Agency: JDI Patent
- Agent Joshua D. Isenberg
- Main IPC: G06F9/455
- IPC: G06F9/455

Abstract:
In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain.
Public/Granted literature
- US20110238403A1 TRANSLATION BLOCK INVALIDATION PREHINTS IN EMULATION OF A TARGET SYSTEM ON A HOST SYSTEM Public/Granted day:2011-09-29
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