In a data processing system, access to a cache in response to access requests from first processing circuitry and snoop requests resulting from a transaction performed by second processing circuitry are arbitrated. Accesses to the cache are monitored to determine if the first processing circuitry is prevented from accessing the cache for more than a threshold amount of time. A signal is generated to indicate when the first processing circuitry has been prevented from accessing the cache for more than the threshold amount of time.