The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a phase of a second clock signal. The first counter generates first count signals and adjusts the first count signals when the phase detector indicates that the phases of the first and the second clock signals are out of alignment. The second counter generates second count signals. The first comparator generates a first comparison signal in response to a comparison between the first count signals and the second count signals. The second clock signal is generated in response to the first comparison signal.