A circuit board process is provided. In the circuit board process, a first substrate and a second substrate are stacked to form a cavity for accommodating chips. The top of the cavity is covered by a third metal layer that serves as a mask. The first substrate has a base, a first metal layer, a second metal layer, and at least a first conductive structure, and the first metal layer is patterned to form a first circuit layer having a number of first pads. The second substrate, at least an insulation layer and a third metal layer are laminated to the first substrate with a common opening in-between, and the third metal layer covers the common opening. A third circuit layer having a number of third pads is formed on the second substrate. The first pads and the third pads are not on a same plane for wire bonding.