Invention Grant
US08133772B2 Deep trench capacitor for SOI CMOS devices for soft error immunity
有权
用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
- Patent Title: Deep trench capacitor for SOI CMOS devices for soft error immunity
- Patent Title (中): 用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
-
Application No.: US13075271Application Date: 2011-03-30
-
Publication No.: US08133772B2Publication Date: 2012-03-13
- Inventor: John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
- Applicant: John E. Barth, Jr. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/8242
- IPC: H01L21/8242
Abstract:
A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
Public/Granted literature
- US20110177660A1 DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY Public/Granted day:2011-07-21
Information query
IPC分类:
