A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. A gate electrode level region is formed above the substrate portion to include conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent are fabricated from respective originating layout features separated from each other by an end-to-end spacing of substantially equal and minimum size across the gate electrode level region. A width of the conductive features within a 5 wavelength photolithographic interaction radius is less than a 193 nanometer wavelength of light used in a photolithography process for their fabrication. Some conductive features extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.