Invention Grant
US08134185B2 Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
有权
具有栅极电平区域的集成电路，其包括至少七个线性形状的导电结构，其等间距包括形成两种不同类型的晶体管的线性导电结构和至少三个具有对齐端的线形导电结构
- Patent Title: Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
- Patent Title (中): 具有栅极电平区域的集成电路，其包括至少七个线性形状的导电结构，其等间距包括形成两种不同类型的晶体管的线性导电结构和至少三个具有对齐端的线形导电结构
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Application No.: US12567654Application Date: 2009-09-25
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Publication No.: US08134185B2Publication Date: 2012-03-13
- Inventor: Scott T. Becker , Michael C. Smayling
- Applicant: Scott T. Becker , Michael C. Smayling
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L27/10
- IPC: H01L27/10
Abstract:
A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout corresponding to an entire gate level of the cell. The gate electrode layout includes a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
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