Invention Grant
- Patent Title: Layered chip package
- Patent Title (中): 分层芯片封装
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Application No.: US12923118Application Date: 2010-09-02
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Publication No.: US08134229B2Publication Date: 2012-03-13
- Inventor: Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
- Applicant: Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki
- Applicant Address: US CA Milpitas JP Tokyo
- Assignee: Headway Technologies, Inc.,TDK Corporation
- Current Assignee: Headway Technologies, Inc.,TDK Corporation
- Current Assignee Address: US CA Milpitas JP Tokyo
- Agency: Oliff & Berridge, PLC
- Main IPC: H01L23/02
- IPC: H01L23/02
Abstract:
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.
Public/Granted literature
- US20100327464A1 Layered chip package Public/Granted day:2010-12-30
Information query
IPC分类:
