Invention Grant
- Patent Title: Leveraging low-latency memory access
- Patent Title (中): 利用低延迟内存访问
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Application No.: US12269877Application Date: 2008-11-12
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Publication No.: US08135723B2Publication Date: 2012-03-13
- Inventor: Kushagra V. Vaid , Gaurav Sareen
- Applicant: Kushagra V. Vaid , Gaurav Sareen
- Applicant Address: US WA Redmond
- Assignee: Microsoft Corporation
- Current Assignee: Microsoft Corporation
- Current Assignee Address: US WA Redmond
- Main IPC: G06F7/00
- IPC: G06F7/00

Abstract:
Computational units of any task may run in different silos. In an embodiment, a search query may be evaluated efficiently on a non-uniform memory architecture (NUMA) machine, by assigning separate chunks of the index to separate memories. In a NUMA machine, each socket has an attached memory. The latency time is low or high, depending on whether a processor accesses data in its attached memory or a different memory. Copies of an index manager program, which compares a query to an index, run separately on different processors in a NUMA machine. Each instance of the index manager compares the query to the index chunk in the memory attached to the processor on which that instance is running. Thus, each instance of the index manager may compare a query to a particular portion of the index using low-latency accesses, thereby increasing the efficiency of the search.
Public/Granted literature
- US20100121865A1 LEVERAGING LOW-LATENCY MEMORY ACCESS Public/Granted day:2010-05-13
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