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US08135768B2 Adder with reduced capacitance 有权
具有降低电容的加法器

Adder with reduced capacitance
Abstract:
An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.
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