Invention Grant
- Patent Title: Adder with reduced capacitance
- Patent Title (中): 具有降低电容的加法器
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Application No.: US11364915Application Date: 2006-03-01
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Publication No.: US08135768B2Publication Date: 2012-03-13
- Inventor: Malcolm Stewart
- Applicant: Malcolm Stewart
- Applicant Address: KR Seoul
- Assignee: Mtekvision Co., Ltd.
- Current Assignee: Mtekvision Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: G06F7/50
- IPC: G06F7/50

Abstract:
An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.
Public/Granted literature
- US20060235924A1 Electronic circuit Public/Granted day:2006-10-19
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