Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm and mapping the design onto hardware. In an aspect, the present invention discloses circuit operation level optimization for data flow graph representations with optimizing zero inputs caused by the upsamplers, or with optimizing unused outputs caused by the downsamplers. In at least one embodiment of the present invention, multirate data graph is converted to a single rate data graph before data flow optimizing. In an aspect, converting a multirate data graph to a single rate data graph comprises unfolding the multirate data graph with minimum unfolding factors that are inversely proportional to the clock values.