Invention Grant
US08136069B2 Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction
有权
在存在灾难性光学接近校正的情况下，在具有不规则偏置的线中的电阻的精确近似和VLSI布局中的互连电容的确定
- Patent Title: Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction
- Patent Title (中): 在存在灾难性光学接近校正的情况下，在具有不规则偏置的线中的电阻的精确近似和VLSI布局中的互连电容的确定
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Application No.: US12423387Application Date: 2009-04-14
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Publication No.: US08136069B2Publication Date: 2012-03-13
- Inventor: Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
- Applicant: Lewis William Dewey, III , Ibrahim M. Elfadel , David J. Widiger
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yee & Associates, P.C.
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
The Width Bias Calculator (WBC) calculates electrical values by effectively averaging the electrical values to either side of a target wire shape whereby values are approximated for design validation without a significant impact on performance or memory consumption.
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