Invention Grant
- Patent Title: Low resistance integrated MOS structure
- Patent Title (中): 低电阻集成MOS结构
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Application No.: US12135956Application Date: 2008-06-09
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Publication No.: US08148754B2Publication Date: 2012-04-03
- Inventor: Maud Pierrel , Bilal Manai
- Applicant: Maud Pierrel , Bilal Manai
- Applicant Address: FR Rousset
- Assignee: Atmel Rousset S.A.S.
- Current Assignee: Atmel Rousset S.A.S.
- Current Assignee Address: FR Rousset
- Agency: Fish & Richardson P.C.
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.
Public/Granted literature
- US20090302393A1 LOW RESISTANCE INTEGRATED MOS STRUCTURE Public/Granted day:2009-12-10
Information query
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