Invention Grant
- Patent Title: Stacked field effect transistor configurations
- Patent Title (中): 堆叠场效应晶体管配置
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Application No.: US12424686Application Date: 2009-04-16
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Publication No.: US08148815B2Publication Date: 2012-04-03
- Inventor: Dev A. Girdhar , Thomas A. Jochum , Bogdan M. Duduman
- Applicant: Dev A. Girdhar , Thomas A. Jochum , Bogdan M. Duduman
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas, Inc.
- Current Assignee: Intersil Americas, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H01L23/24
- IPC: H01L23/24

Abstract:
An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area ‘footprint’ of the MOSFET pair. The source and drain of a high side FEThigh and a low side FETlow or the drains of the respective high side FEThigh and low side FETlow are bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.
Public/Granted literature
- US20100090668A1 Stacked Field Effect Transistor Configurations Public/Granted day:2010-04-15
Information query
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