Invention Grant
- Patent Title: Quad flat no lead (QFN) package
- Patent Title (中): 四边形无铅(QFN)封装
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Application No.: US12832223Application Date: 2010-07-08
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Publication No.: US08148827B2Publication Date: 2012-04-03
- Inventor: Yu-Tang Pan , Shih-Wen Chou
- Applicant: Yu-Tang Pan , Shih-Wen Chou
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technologies Inc.
- Current Assignee: Chipmos Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King
- Priority: TW98146106A 20091231
- Main IPC: H01L23/49
- IPC: H01L23/49

Abstract:
The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention.
Public/Granted literature
- US20110156281A1 Quad Flat No Lead (QFN) Package Public/Granted day:2011-06-30
Information query
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