Invention Grant
- Patent Title: Voltage regulator circuit
- Patent Title (中): 稳压电路
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Application No.: US12662371Application Date: 2010-04-13
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Publication No.: US08148960B2Publication Date: 2012-04-03
- Inventor: Fumio Tonomura
- Applicant: Fumio Tonomura
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-102964 20090421
- Main IPC: G05F1/00
- IPC: G05F1/00

Abstract:
It is desired for semiconductor devices to reduce an inrush current and an overshoot. According to the voltage regulator circuit of the present invention, when a power supply is turned on, a switch SW1 is turned on in response to a control signal CTR1, a switch SW2 is turned off, and a reference voltage Vref is input to the first (+IN) and second (−IN) inputs of a differential amplifier AMP1 as a common voltage. When a common voltage is supplied to the first (+IN) and second (−IN) inputs, the current I flows into a smoothing capacitor C1 from the high-voltage power supply (VDD) via the differential amplifier AMP1 is regulated to be small. Namely, an inrush current can be reduced. Further, according to the voltage regulator circuit 30 of the present invention, the increase of the output voltage Vout from the differential amplifier AMP1 is relaxed so that the overshoot can be suppressed.
Public/Granted literature
- US20100264896A1 Voltage regulator circuit Public/Granted day:2010-10-21
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