The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.