Invention Grant
US08149884B2 Jitter buffer control method and communication apparatus 失效
抖动缓冲器控制方法和通信装置

  • Patent Title: Jitter buffer control method and communication apparatus
  • Patent Title (中): 抖动缓冲器控制方法和通信装置
  • Application No.: US12509625
    Application Date: 2009-07-27
  • Publication No.: US08149884B2
    Publication Date: 2012-04-03
  • Inventor: Shuji Teramoto
  • Applicant: Shuji Teramoto
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2008-196672 20080730
  • Main IPC: H04J3/06
  • IPC: H04J3/06
Jitter buffer control method and communication apparatus
Abstract:
Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit.
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