A path redundant, hardware efficient communications interconnect (1) has embodiments that can present true any-to-any interconnect capability for first and second pathways (2) and (3) and can utilize double throw switches (25) with or without single throw switches (24) perhaps in staged collectives of sub arrays (4), (5), (6), (9), and (10). A loop-back communications interconnect (22) can be accomplished by an interleaved sub array (26). A quadrilateral center stage sub array (21) can be combined with asymmetric side stage sub arrays for hardware savings that are tenths of a percent of a traditional interconnect and even present eight fold savings over prior reduced hardware interconnects.