An image pipeline device is used for processing an image. The device comprises an external memory, a direct memory access (DMA), an image pipeline controller, and a filter layer. The image pipeline controller comprises a physical memory allocation (PMA) having a physical buffer unit, and a first array controller for configuring the physical buffer unit as a corresponding first logic buffer unit. The filter layer comprises a first filter set electrically connected to the first array controller correspondingly and having a plurality of filters. The first filter set receives the image through the first array controller, processes the image selectively according to the first logic buffer unit and the filters, and stores the processed image back to the external memory through the DMA.