Invention Grant
US08151081B2 Method, system and apparatus for memory address mapping for sub-socket partitioning
有权
用于子插槽分区的内存地址映射的方法，系统和设备
- Patent Title: Method, system and apparatus for memory address mapping for sub-socket partitioning
- Patent Title (中): 用于子插槽分区的内存地址映射的方法，系统和设备
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Application No.: US12291303Application Date: 2008-11-07
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Publication No.: US08151081B2Publication Date: 2012-04-03
- Inventor: Ajay Harikumar , Tessil Thomas , Biju Puthur Simon
- Applicant: Ajay Harikumar , Tessil Thomas , Biju Puthur Simon
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Priority: IN2675/DEL/2007 20071220
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.
Public/Granted literature
- US20090164747A1 Method,system and apparatus for memory address mapping for sub-socket partitioning Public/Granted day:2009-06-25
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