Invention Grant
US08151089B2 Array-type processor having plural processor elements controlled by a state control unit
有权
具有由状态控制单元控制的多个处理器单元的阵列型处理器
- Patent Title: Array-type processor having plural processor elements controlled by a state control unit
- Patent Title (中): 具有由状态控制单元控制的多个处理器单元的阵列型处理器
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Application No.: US10694822Application Date: 2003-10-29
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Publication No.: US08151089B2Publication Date: 2012-04-03
- Inventor: Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
- Applicant: Taro Fujii , Koichiro Furuta , Masato Motomura , Kenichiro Anjo , Yoshikazu Yabe , Toru Awashima , Takao Toi , Noritsugu Nakamura
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2002-315735 20021030
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F15/76
Abstract:
A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.
Public/Granted literature
- US20040107332A1 Array-type processor Public/Granted day:2004-06-03
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