Invention Grant
US08151152B2 Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method 有权
锁存电路包括数据输入端和扫描数据输入端,以及半导体器件及控制方法

  • Patent Title: Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method
  • Patent Title (中): 锁存电路包括数据输入端和扫描数据输入端,以及半导体器件及控制方法
  • Application No.: US12607627
    Application Date: 2009-10-28
  • Publication No.: US08151152B2
    Publication Date: 2012-04-03
  • Inventor: Katsunao Kanari
  • Applicant: Katsunao Kanari
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Priority: JP2008-287186 20081107
  • Main IPC: G01R31/28
  • IPC: G01R31/28
Latch circuit including data input terminal and scan data input terminal, and semiconductor device and control method
Abstract:
A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan clock input terminal, a logical circuit that performs a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generates an update clock and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holds the data or the scan data provided from the update input terminal when the update clock is provided.
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