• Patent Title: Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
  • Application No.: US11987811
    Application Date: 2007-12-04
  • Publication No.: US08151226B2
    Publication Date: 2012-04-03
  • Inventor: Yoshiyuki KatoHisashi AoyamaMitsuru Sato
  • Applicant: Yoshiyuki KatoHisashi AoyamaMitsuru Sato
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Priority: JP2006-327388 20061204; JP2006-327389 20061204; JP2006-327390 20061204; JP2006-327391 20061204; JP2006-327392 20061204; JP2007-305868 20071127; JP2007-305869 20071127; JP2007-305870 20071127; JP2007-305871 20071127; JP2007-305872 20071127
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
Abstract:
An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.
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