Invention Grant
- Patent Title: Circuit design with incremental simultaneous switching noise analysis
- Patent Title (中): 电路设计采用增量同时开关噪声分析
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Application No.: US12419518Application Date: 2009-04-07
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Publication No.: US08151233B1Publication Date: 2012-04-03
- Inventor: Navid Azizi , Joshua David Fender
- Applicant: Navid Azizi , Joshua David Fender
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble Carlyle Sandridge & Rice LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods, computer programs, and systems for designing an electronic component are presented. One method calculates a first Simultaneous Switching Noise (SSN) on Input/Output (IO) pins using a first configuration of the electronic component. A setting or a placement of a chosen IO pin is changed to obtain a second configuration of the electronic component, and a second SSN on IO pins is obtained based on the results of the first SSN and based on new SSN calculations related to the changed setting or placement. The second SSN on an IO pin, other than the chosen IO pin, is calculated by subtracting from the first SSN on the IO pin the SSN caused by the chosen IO pin calculated in the first SSN, and by adding an incremental SSN caused by the chosen IO pin on the pin in the second configuration. The method further includes the operation of creating a design for the electronic component with either the first or the second configuration based on the results of the first and the second SSN.
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