Invention Grant
- Patent Title: Semiconductor integrated circuit and design method thereof
- Patent Title (中): 半导体集成电路及其设计方法
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Application No.: US12943549Application Date: 2010-11-10
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Publication No.: US08151238B2Publication Date: 2012-04-03
- Inventor: Kouji Fujiyama , Takahiro Nagatani , Atsushi Takahashi
- Applicant: Kouji Fujiyama , Takahiro Nagatani , Atsushi Takahashi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-339684 20051125; JP2006-156490 20060605
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455 ; H01L25/00 ; H01L27/118 ; H01L23/52

Abstract:
In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.
Public/Granted literature
- US20110057320A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGN METHOD THEREOF Public/Granted day:2011-03-10
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