Invention Grant
US08154069B2 NAND flash memory with selection transistor having two-layer inter-layer insulation film
失效
具有选择晶体管的NAND闪存具有两层层间绝缘膜
- Patent Title: NAND flash memory with selection transistor having two-layer inter-layer insulation film
- Patent Title (中): 具有选择晶体管的NAND闪存具有两层层间绝缘膜
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Application No.: US11845376Application Date: 2007-08-27
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Publication No.: US08154069B2Publication Date: 2012-04-10
- Inventor: Mutsuo Morikado
- Applicant: Mutsuo Morikado
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-231145 20060828
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode.
Public/Granted literature
- US20080048243A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF Public/Granted day:2008-02-28
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