Invention Grant
- Patent Title: Solder bump, semiconductor chip, method of manufacturing the semiconductor chip, conductive connection structure, and method of manufacturing the conductive connection structure
- Patent Title (中): 焊接凸块,半导体芯片,制造半导体芯片的方法,导电连接结构以及导电连接结构的制造方法
-
Application No.: US12707872Application Date: 2010-02-18
-
Publication No.: US08154123B2Publication Date: 2012-04-10
- Inventor: Shigeru Kondou , Yoshihiro Tomura
- Applicant: Shigeru Kondou , Yoshihiro Tomura
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Hamre, Schumann, Mueller & Larson, P.C.
- Priority: JP2009-037258 20090220; JP2010-028342 20100212
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 5 is contained in a solder bump 6 and a solder joint 17 which connect a connection electrode 3 of a semiconductor chip 2 and a substrate 11, and the filler has a larger density on the side of the connection electrode 3 than on the side of the substrate 11 in the solder joint 17. Therefore, in the cooling solidification of solder, the shrinkage of the solder joint 17 near the connection electrode 3 of the semiconductor chip 2 is reduced by the filler 5 and the occurrence of a stress is reduced on the peripheral portion of the connection electrode 3, thereby preventing the occurrence of cracks near the joint.
Public/Granted literature
Information query
IPC分类: