A phase detector circuit generates a phase comparison signal based on a phase difference between first and second periodic signals during a test mode. Phases of the first and the second periodic signals do not change in response to variations in a signal generated by the phase detector circuit during the test mode. A lock generation circuit generates an output signal based on the phase comparison signal that indicates if the first and the second periodic signals are within a lock window of the lock generation circuit. The lock window of the lock generation circuit changes in response to a variation in a control signal.