Invention Grant
US08154330B2 Delay line calibration mechanism and related multi-clock signal generator 有权
延时线校准机制及相关多时钟信号发生器

  • Patent Title: Delay line calibration mechanism and related multi-clock signal generator
  • Patent Title (中): 延时线校准机制及相关多时钟信号发生器
  • Application No.: US12437563
    Application Date: 2009-05-08
  • Publication No.: US08154330B2
    Publication Date: 2012-04-10
  • Inventor: Hong-Sing KaoMeng-Ta YangTse-Hsiang Hsu
  • Applicant: Hong-Sing KaoMeng-Ta YangTse-Hsiang Hsu
  • Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
  • Assignee: Mediatek Inc.
  • Current Assignee: Mediatek Inc.
  • Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
  • Agent Winston Hsu; Scott Margo
  • Main IPC: H03L7/00
  • IPC: H03L7/00
Delay line calibration mechanism and related multi-clock signal generator
Abstract:
A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse.
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