Invention Grant
- Patent Title: Nonvolatile memory circuit using spin MOS transistors
- Patent Title (中): 使用自旋MOS晶体管的非易失性存储电路
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Application No.: US12889881Application Date: 2010-09-24
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Publication No.: US08154916B2Publication Date: 2012-04-10
- Inventor: Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
- Applicant: Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-25821 20100208
- Main IPC: G11C11/14
- IPC: G11C11/14

Abstract:
Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
Public/Granted literature
- US20110194342A1 NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS Public/Granted day:2011-08-11
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