Invention Grant
US08156355B2 Systems and methods for reducing static and total power consumption 失效
降低静态和总功耗的系统和方法

Systems and methods for reducing static and total power consumption
Abstract:
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
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