Invention Grant
- Patent Title: Data controlling in the MBIST chain architecture
- Patent Title (中): MBIST链架构中的数据控制
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Application No.: US12167305Application Date: 2008-07-03
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Publication No.: US08156391B2Publication Date: 2012-04-10
- Inventor: Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
- Applicant: Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agent Christopher P. Maiorana, PC
- Main IPC: G11C29/14
- IPC: G11C29/14 ; G11C29/50
Abstract:
A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
Public/Granted literature
- US20090300440A1 DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE Public/Granted day:2009-12-03
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