Invention Grant
- Patent Title: Device and technique for transistor well biasing
- Patent Title (中): 晶体管阱偏置的器件和技术
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Application No.: US12115825Application Date: 2008-05-06
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Publication No.: US08164378B2Publication Date: 2012-04-24
- Inventor: Stefano Pietri , Alfredo Olmos , Jehoda Refaeli , Jefferson Daniel de Barros Soldera
- Applicant: Stefano Pietri , Alfredo Olmos , Jehoda Refaeli , Jefferson Daniel de Barros Soldera
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H03K3/01
- IPC: H03K3/01 ; H03K17/00

Abstract:
A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.
Public/Granted literature
- US20090278571A1 DEVICE AND TECHNIQUE FOR TRANSISTOR WELL BIASING Public/Granted day:2009-11-12
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