An integrated circuit (102) and method computes fixed point vector dot products (424) and/or matrix vector products using a type of distributed architecture that loads bit planes (add 00-add30) and uses the loaded bit planes to generate a plurality of partial products (416-422) directly, such as without a lookup table, and the plurality of partial products are computed in real time and are not read out of addressable memory. In one example, pixel coefficients and corresponding data are loaded such that, for example, a bit plane is loaded to generate partial product results on a per bit plane basis. The plurality of partial products are then summed (414) or accumulated to produce fixed point vector dot product data (424).