Invention Grant
US08165260B2 Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique
有权
用于数字PLL和HF分频器的环路带宽增强技术，可实现此技术
- Patent Title: Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique
- Patent Title (中): 用于数字PLL和HF分频器的环路带宽增强技术，可实现此技术
-
Application No.: US13046523Application Date: 2011-03-11
-
Publication No.: US08165260B2Publication Date: 2012-04-24
- Inventor: Krishnaswamy Nagaraj , Karthik Subburaj
- Applicant: Krishnaswamy Nagaraj , Karthik Subburaj
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24
Abstract:
A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.
Public/Granted literature
- US20110158368A1 LOOP BANDWIDTH ENHANCEMENT TECHNIQUE FOR A DIGITAL PLL AND A HF DIVIDER THAT ENABLES THIS TECHNIQUE Public/Granted day:2011-06-30
Information query
IPC分类:
