Invention Grant
US08165706B2 Methods for generating representations of flatness defects on wafers
有权
用于产生晶片上的平坦度缺陷表示的方法
- Patent Title: Methods for generating representations of flatness defects on wafers
- Patent Title (中): 用于产生晶片上的平坦度缺陷表示的方法
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Application No.: US12648613Application Date: 2009-12-29
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Publication No.: US08165706B2Publication Date: 2012-04-24
- Inventor: John A. Pitney
- Applicant: John A. Pitney
- Applicant Address: US MO St. Peters
- Assignee: MEMC Electronic Materials, Inc.
- Current Assignee: MEMC Electronic Materials, Inc.
- Current Assignee Address: US MO St. Peters
- Agency: Armstrong Teasdale LLP
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
Public/Granted literature
- US20110160890A1 Methods For Generating Representations of Flatness Defects on Wafers Public/Granted day:2011-06-30
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